(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of shallow trench isolations in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
The use of shallow trench isolation (STI) for the formation of integrated circuit isolations has grown in the art due to the reduced surface area and improved topology of STI when compared to traditional local oxidation of silicon (LOCOS) schemes. One problem that is encountered in the use of STI is oxide dishing.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit is shown. A semiconductor substrate 10 is shown. A trench has been etched into the surface of the semiconductor substrate 10. An isolation oxide layer 14 fills the trenches. A chemical mechanical polish (CMP) was used to polish down the isolation oxide layer 14 to the top surface of the silicon substrate 10 to complete the shallow trench isolations. Following the polish, however, significant dishing 18 has occurred.
Oxide dishing occurs, in part, due to pad deformation in the chemical mechanical polish (CMP) process used to planarize the STI structures. Dishing is especially pronounced on large or wide STI structures because the isolation oxide over these trenches is typically thinner than the oxide deposited over narrow trenches due to topological effects. Narrower STI structures may demonstrate little or no dishing. This dishing 18 can cause increased current leakage and decreased gate oxide voltage breakdown. These problems at the active area interface reduce device yield.
Referring now to FIG. 2, a second prior art integrated circuit demonstrates a second potential problem. Again, a trench has been etched into the surface of a semiconductor substrate 20. An isolation oxide layer 24 is again deposited in the trench. In this case, no CMP process is used to remove the excess oxide. Therefore, the isolation oxide layer 24 is left protruding above the surface of the semiconductor substrate 20. This topology creates corners 28 on the STI. During the subsequent formation of sidewall spacers on the transistor gates, in the case of a MOS process, parasitic spacers will also form on these STI sidewalls 28. These parasitic spacers will reduce the device active area and can cause problems in forming drain or source contacts.
Several prior art approaches disclose methods to create isolation regions in the silicon substrate. U.S. Pat. No. 5,087,586 to Chan et al teaches a process to form shallow trench isolations. Temporary silicon nitride or combination silicon nitride and silicon dioxide sidewall spacers are formed on trench sidewalls. Silicon is epitaxially grown in the trenches. The sidewall spacers are then removed. A trench oxide fill layer is deposited to completely fill the trenches. Because the trench oxide fill layer is deposited by a conformal CVD process, a final polish down is required to planarize the area. U.S. Pat. No. 5,236,863 to Iranmanesh teaches a method to form shallow trench isolations. A three-layer stack of silicon dioxide, silicon nitride, and silicon dioxide is formed over the substrate. The top silicon dioxide layer is used as a required hard mask in the trench etch process. After trench etching and preparation, a thin oxide is optionally grown over the silicon trench fill layer. A thicker oxide layer is then deposited. A photoresist layer is deposited. A planarizing etch must be performed due to the conformal deposition process used to deposit the thicker oxide layer. This method forms an oxide layer between spacers. U.S. Pat. No. 5,472,903 to Lur et al discloses a process to form isolations. An oxide over nitride over oxide stack is formed over the substrate. Trenches are etched through the stack and into the substrate. Polysilicon columns are formed inside the trenches using temporary nitride columns in the process. The polysilicon columns are oxidized to form a silicon dioxide filler for the trenches. U.S. Pat. No. 5,387,538 to Moslehi teaches a method to form trench isolations. Trenches are etched into the substrate and then lined with oxide. The trench is lined with silicon nitride. A polysilicon or amorphous silicon layer is deposited over the nitride. Temporary sidewalls are then formed in the trenches. A silicon island is grown in the trenches over the polysilicon or amorphous silicon layer. The temporary spacers are then removed. The silicon island is then completely oxidized to form the trench filler. U.S. Pat. No. 5,496,765 to Schwalke and U.S. Pat. No. 5,416,041 to Schwalke disclose processes to form trench isolations in a silicon on insulator (SOI) process. U.S. Pat. No. 5,668,043 to Park discloses a method to form field oxide (FOX) regions using a transitional metal spacer to create peripheral trenches. U.S. Pat. No. 5,888,881 to Jeng et al teaches a process to form field oxide regions. A polysilicon or amorphous silicon layer is oxidized to form the filler for narrow trenches in this process. U.S. Pat. No. 5,212,110 to Pfiester et al discloses a trench isolation method using a silicon germanium layer.